Huawei stacked two logic layers in its 2026 Kirin design, with chief semiconductor scientist Liao Heng saying the dies are joined by roughly 50 million vertical connections, an approach that recovers performance through packaging rather than smaller transistors. China imposed provisional anti-dumping duties on Japanese dichlorosilane, requiring importers to post security deposits from today on a chipmaking gas that also feeds Chinese fabrication lines, after preliminarily finding dumping margins of 80.8% to 99.2%. China's Supreme People's Court set AI liability rules, telling lower courts they may clear open-source AI developers of liability for a user's infringement when the code was supplied free of charge and the developer publicly explained the model's functions and safety risks.
Huawei chief semiconductor scientist Liao Heng said the company's 2026 Kirin design forms about 50 million vertical connections between two stacked dies, of which 5 million to 10 million carry signals. Recovering performance by stacking logic instead of shrinking transistors shifts the question from which manufacturing generation Chinese foundries can reach to how much a designer can extract from the ones already available. Conventional 3D packaging places tens of thousands to a few hundred thousand connections between two dies, Liao said. The part is the Kirin 9050 Pro, which Huawei calls its first logic-folded chip and debuted in the Mate XT 2 tri-fold phone. Chu Junhao, a semiconductor physicist at the Chinese Academy of Sciences, said work across materials, thermal management and packaging still has to follow. Huawei last unveiled a new flagship Kirin part at a launch event with the Mate 40 in 2020.
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